The present invention relates generally to nonvolatile circuits, and more particularly to nonvolatile circuits that may be programmed to recall one or more particular states.
Integrated circuit devices may include volatile and nonvolatile circuit elements. As is well known, volatile circuit elements are typically not capable of retaining a particular state in the absence of power. In contrast, nonvolatile circuits can retain one of at least two states in the absence of power. Nonvolatile circuit elements may include, without limitation, various erasable programmable read-only-memory cells (such as EPROMs, conventional EEPROMs, and xe2x80x9cflashxe2x80x9d EEPROMs). A typical EPROM cell can take advantage of a charge storing structure, such as a floating gate, a charge storing dielectric and/or a charge-trapping interface of materials. Alternate nonvolatile structures may take advantage of other materials, such as ferroelectric materials, or the like.
One concern with many nonvolatile circuit elements can be variations in response over time. In particular, a nonvolatile circuit element may include a field effect transistor having a threshold voltage that may be set to at least two states. Such a field effect transistor may have a charge storing structure (e.g., a floating gate or charge storing dielectric), and can be programmed to one threshold voltage and erased to another threshold voltage. Typically, an erased threshold voltage is less than a programmed threshold voltage.
Unfortunately, a nonvolatile transistor threshold voltage can change over time. Such changes can arise due to xe2x80x9cdisturbsxe2x80x9d caused by local fields generated on a device. In addition, charge may leak from a charge storing structure. If a threshold voltage changes a sufficient amount, an erased threshold may be misread as a programmed voltage, or vice versa.
Typically, conventional volatile circuits may provide a more rapid response than nonvolatile circuits. Thus, data may be written to conventional volatile circuit elements faster than it can be stored (programmed) into conventional nonvolatile circuit elements.
While conventional volatile circuits can typically operate with acceptable reliability, in most environments, it can be advantageous to add nonvolatile functionality to a circuit. For example, in some applications, a device may be subject to unwanted interruptions in power. In such a case, it may be advantageous to preserve a circuit state or pre-programmed data so that circuit operation may resume once power is returned.
One example of a circuit that may provide both rapid operation and a form of nonvolatility is a nonvolatile (NV) static random access memory (SRAM) cell. A NVSRAM cell may have data stored (or programmed). The NVSRAM cell may then operate in a conventional SRAM manner by receiving data values according to write operations and providing data values according to read operations.
Unlike volatile SRAM cells, a NVSRAM cell may further include a recall operation. In a recall operation, a NVSRAM cell can be forced to the state established in a previous store operation. Such an arrangement can allow stored data to be preserved in the event that power is interrupted. More particularly, if a power interruption is detected, a limited amount of back up power can be made available to store the current state of a volatile SRAM circuit in nonvolatile circuit elements.
One example of a conventional NVSRAM cell is shown in FIG. 6 and designated by the general reference character 600. A conventional NVSRAM cell 600 may include a volatile section 602 and a nonvolatile section 604. A volatile section 602 may include a conventional six-transistor (6-T) memory cell with cross-coupled complementary driver transistors 606/608 and 610/612. A first data node 614 may be formed between drains of transistors 606 and 608, while a second data node 616 may be formed between drains of transistors 610 and 612. First and second data nodes (614 and 616) can store complementary data values that may be accessed by access transistors 618 and 620.
A conventional NVSRAM cell 600 can differ from a typical SRAM cell in that complementary data nodes (614 and 616) may be connected to a nonvolatile portion 604. Such an arrangement can enable a data value stored in a volatile section 602 to be programmed into a nonvolatile section 604. Such programmed data in a nonvolatile section 604 may then be recalled into a volatile section 602.
In an arrangement such as that shown in FIG. 6, a nonvolatile section 604 may include a pair of nonvolatile devices 622 and 624 that may be programmed to complementary states. More particularly, nonvolatile devices 622 and 624 can be silicon-oxide-nitride-oxide-silicon (SONOS) transistors that may be programmed to different threshold voltages. Nonvolatile devices (622 and 624) may be connected to a volatile section 602 by a load path that includes load devices 626 and 628 and a program path that includes program devices 630 and 632.
A load path (626 and 628) may be used to connect nonvolatile devices (622 and 624) to a volatile section 602 in a recall operation. More particularly, nonvolatile devices 622 and 624 that are programmed to different threshold voltages can be connected to data nodes (614 and 616) so that one data node can be lower than the other as a power supply to the volatile section 602 is ramped up. A conventional NVSRAM 600 may thus rely on two nonvolatile devices (622 and 624) set to different states.
A program path (630 and 632) may be used to connect nonvolatile devices (622 and 624) to a volatile section 602 in a store operation. More particularly, nonvolatile devices 622 and 624 may be initially erased. Complementary values at data nodes (614 and 616) may then be used to program nonvolatile devices 624 or 622, respectively, to different threshold voltages.
As shown in FIG. 6, a program path (630 and 632) connection to data nodes 616 and 614, respectively, can have a crossover with respect to a load path (626 and 628) to data nodes (614 and 616). Such an arrangement may be included because a set of data node values used to program nonvolatile devices (622 or 624) can result in an opposite set of data values being recalled from the nonvolatile devices (622 or 624).
A nonvolatile section 604 may also include programming devices 634 and 636, which can connect a programming voltage to nonvolatile devices (622 and 624) in a program operation and a ground connection during a non-volatile recall.
A drawback to conventional arrangements, like that shown in FIG. 6, can be the number of devices included in the circuit. As noted above, a conventional NVSRAM 600 may include two nonvolatile devices as it can rely on programming such devices to different states. Further, because two nonvolatile devices can be used, a program path (630 and 632) and load path (626 and 628) may include two devices. Such devices can increase the overall area required for a NVSRAM cell. A larger cell area can work against the goal of reducing overall die size. Smaller die sizes are desirable, as they can allow for more economical manufacturing of integrated circuits.
It is understood that a NVSRAM 600 could also include additional circuit elements, including but not limited to xe2x80x9choldxe2x80x9d devices (634 and 636) that may isolate p-channel driver devices (606 and 610) from their corresponding n-channel driver devices (608 and 612), an equalization device for equalizing data nodes (614 and 616), and/or dual port circuitry that allows additional access to one or both data nodes (614 and 616).
Having described a xe2x80x9cdifferentialxe2x80x9d approach to a NVSRAM (i..e., two nonvolatile devices programmed to different states), a xe2x80x9csingle-sidexe2x80x9d approach to a NVSRAM will now be described.
Referring now to FIG. 7, another conventional NVSRAM cell is designated by the general reference character 700, and is shown to include a volatile portion 702 and a nonvolatile portion 704. Such a conventional NVSRAM cell is disclosed in U.S. Pat. No. 5,488,579 issued to Sharma et al. on Jan. 30, 1996.
Referring back to FIG. 7, a volatile portion 702 may include a conventional 6-T volatile SRAM as previously described. To that extent, like elements are referred to by the same reference character but with the first digit being a xe2x80x9c7xe2x80x9d instead of an xe2x80x9c6.xe2x80x9d A nonvolatile section 704 may include a nonvolatile device 722, a node isolation device 724 and a supply isolation device 726.
Because a conventional NVSRAM cell 700 represents a one-sided approach, such an NVSRAM may only include one nonvolatile device 722. This can result in a more compact structure than that shown in FIG. 6.
A drawback to a NVSRAM cell 700 can be additional circuitry and/or complexity that may be required to execute various functions. More particularly, it is not clear how back-to-back store/recall operations can occur without inverting data values. It appears that a store operation may include writing the opposite value of what is to be recalled, or various unconventional voltage arrangements, such as a negative voltage during recall or a very high positive voltage during programming.
For example, it will be assumed that in a store operation, node 716 is high, while node 714 is low. With node 716 high, a gate of a supply isolation device 726 can be high while a gate of node isolation device 724 can be low. A gate of nonvolatile device 722 may then initially transition low, and then transition high. An initial low voltage at a gate of nonvolatile device 722 in conjunction with a high voltage at node 716 can result in nonvolatile device 722 being programmed, as an electric field may enable electrons to tunnel from a charge storing layer to a substrate or transistor channel, source and/or drain region.
Because node 716 is already high, when a gate of nonvolatile device 722 transition high, an electric field across a tunneling dielectric can be sufficiently small to prevent significant tunneling from a substrate or transistor channel, source and/or drain region, to a charge storing layer. This can increase a threshold voltage of a nonvolatile device 722.
It is noted that if a recall operation immediately follows the previously described store operation, node 716 can have an opposite value to that used in programming. In a recall operation, the gates of a node isolation device 724 and supply isolation device 726 can be low. Consequently, a potential at data node 716 can depend upon a threshold voltage of a nonvolatile device 722. However, because a nonvolatile device 722 was previously programmed, the description of the device implies that data node 714 can be driven high, while data node 716 will be driven low. A low data node 716 value is the opposite of the value used to initially program the NVSRAM. Hence, a data value may invert when a store operation is followed by a recall operation.
Another drawback to a NVSRAM cell 700 can be the reliability of a recall cycle. In particular, a volatile portion 702 can remain enabled during a recall operation. Consequently, if a recalled value places a volatile operation in the opposite state to what is currently being stored, a nonvolatile portion 704 may have to xe2x80x9coverpowerxe2x80x9d the current state of a volatile portion 702.
In light of the above drawbacks that may be inherent in conventional nonvolatile circuits, it would be desirable to arrive at a nonvolatile circuit that may have fewer circuit devices than that of FIG. 6, yet not suffer from the drawbacks that may be present in an approach like FIG. 7.
It is also noted that the above-described conventional approaches do not appear to provide a way of testing a nonvolatile device for possible changes in threshold voltage (i.e., perform a margin test). It would thus be desirable to arrive at some way of margin testing a nonvolatile circuit.
According to embodiments of the present invention, a nonvolatile circuit may include a volatile circuit portion and a nonvolatile circuit portion. A nonvolatile circuit portion may be programmed and/or erased to store, in a nonvolatile fashion, a particular state. Such a nonvolatile state may establish the state of a volatile circuit portion in a recall operation. Reduction in circuit components may be achieved by including only one nonvolatile device.
According to one aspect of the embodiments, separate store and recall paths may be provided between a volatile circuit portion and a nonvolatile device. Consequently, a recall operation can be performed after a store operation that does not result in an inversion of data values.
According to another aspect of the embodiments, a nonvolatile device may include a silicon-oxide-nitride-oxide-silicon (SONOS) transistor.
According to another aspect of the embodiments, data nodes in a volatile circuit portion may have complementary logic values. Such data nodes can be connected to a nonvolatile device through store and recall paths.
According to another aspect of the embodiments, in a recall operation a data node can be discharged (or charged) according to the state of a nonvolatile device. A control device may be included that controls the flow of current to a data node.
According to another aspect of the embodiments, a control device may allow margin testing of a nonvolatile device by indicating the amount of current that may be needed to discharge (or charge) a device in a recall operation.
According to another aspect of the embodiments, a control device may isolate a data node from a power supply in a recall operation, allowing for a rapid dynamic recall operation.
According to another aspect of the embodiments, a volatile circuit portion may include a static random access memory (SRAM) circuit.
According to another aspect of the embodiments, a volatile circuit portion may include a flip-flop circuit. Such a flip-flop circuit may include a set-reset flip-flop circuit and/or a D-type set-reset flip-flop circuit.